Hardware design and testing of the generic rear transition module for the global trigger subsystem of ATLAS Phase-II Upgrade

Abstract In the framework of ATLAS experiment’s Phase-II Upgrade at High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware algorithms will be implemented onto a single-level, 10 μs-latency architecture. The Global Trigger is subsystem which bring event-filter capabilities by performing offline-like on full-granularity calorimeter data. implementation functionality firmware-focused composed several processing nodes, are hosted identical hardware, made up an Advanced Telecommunications Computing Architecture (ATCA) front board, called Common Module (GCM), rear transition module (RTM), Generic RTM (GRM). GRM, was developed to mitigate risks deriving from complex design power management GCM, features advanced Xilinx Versal Prime system-on-chip can handle communication with GCM Front-End Link eXchange (FELIX) processors through 124 25.8 Gb/s transceiver links, for readout control. Additionally, GRM mounts Low-Power GigaBit Transceiver (lpGBT) chip enables emulation detector front-ends integration tests. This paper presents its testing.